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<A name="Par"></A>Copyright 2015 Lattice Semiconductor Corporation, All Rights Reserved
Wed Sep 23 23:41:36 2020

Command Line: par -w -n 1 -t 85 -s 1 -cores 1 -exp parPathBased=ON \
	fft_adc_impl_1_map.udb fft_adc_impl_1.udb 


<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/       Number       Worst        Timing       Worst        Timing       Run          Run
Cost [udb]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
<span style="background-color:red">5_85  *      0            -6.390       679312       2.596        0            01:42        Completed</span>
* : Design saved.

Total (real) run time for 1-seed: 1 mins 42 secs 

par done!

Lattice Place and Route Report for Design &quot;fft_adc_impl_1_map.udb&quot;
Wed Sep 23 23:41:36 2020


<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Radiant Software (64-bit) 2.0.0.64.1.
Command Line: par -w -t 85 -cores 1 -exp parPathBased=ON fft_adc_impl_1_map.udb \
	fft_adc_impl_1_par.dir/5_85.udb 

Loading fft_adc_impl_1_map.udb ...
Loading device for application udb from file &apos;itpa08.nph&apos; in environment: /opt/lscc/radiant/2.0/ispfpga.
Design:  top
Family:  iCE40UP
Device:  iCE40UP5K
Package: SG48
Performance Grade:   High-Performance_1.2V
WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_R]&apos; with non-SLICE and non-I/O type instance &apos;LED_R&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_G]&apos; with non-SLICE and non-I/O type instance &apos;LED_G&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_B]&apos; with non-SLICE and non-I/O type instance &apos;LED_B&apos;.

WARNING - par: Unable to find the instance/port &apos;BUT_USER&apos; in the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;, the locate object is not specified

WARNING - par: Unable to find the instance/port &apos;BUT_TRIG&apos; in the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;, the locate object is not specified

WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: There are multiple clocks defined on &apos;hi_clock_gen_inst/CLKHF&apos;. Clock &apos;clk&apos; is used, others are ignored.
WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_R]&apos; with non-SLICE and non-I/O type instance &apos;LED_R&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_G]&apos; with non-SLICE and non-I/O type instance &apos;LED_G&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_B]&apos; with non-SLICE and non-I/O type instance &apos;LED_B&apos;.

WARNING - par: Unable to find the instance/port &apos;BUT_USER&apos; in the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;, the locate object is not specified

WARNING - par: Unable to find the instance/port &apos;BUT_TRIG&apos; in the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;, the locate object is not specified

WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: There are multiple clocks defined on &apos;hi_clock_gen_inst/CLKHF&apos;. Clock &apos;clk&apos; is used, others are ignored.
WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_R]&apos; with non-SLICE and non-I/O type instance &apos;LED_R&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_G]&apos; with non-SLICE and non-I/O type instance &apos;LED_G&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_B]&apos; with non-SLICE and non-I/O type instance &apos;LED_B&apos;.

WARNING - par: Unable to find the instance/port &apos;BUT_USER&apos; in the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;, the locate object is not specified

WARNING - par: Unable to find the instance/port &apos;BUT_TRIG&apos; in the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;, the locate object is not specified

WARNING - par: Top module port &apos;BUT_USER&apos; does not connect to anything.
WARNING - par: Top module port &apos;BUT_TRIG&apos; does not connect to anything.
WARNING - par: Top module port &apos;BUT_USER&apos; does not connect to anything.
WARNING - par: Top module port &apos;BUT_TRIG&apos; does not connect to anything.
WARNING - par: Top module port &apos;BUT_USER&apos; does not connect to anything.
WARNING - par: Top module port &apos;BUT_TRIG&apos; does not connect to anything.
WARNING - par: Top module port &apos;BUT_USER&apos; does not connect to anything.
WARNING - par: Top module port &apos;BUT_TRIG&apos; does not connect to anything.
Number of Signals: 6718
Number of Connections: 18981

<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>

   SLICE (est.)    2162/2640         81% used
     LUT           4149/5280         78% used
     REG           2180/5280         41% used
   PIO               31/56           55% used
                     31/36           86% bonded
   IOLOGIC            0/56            0% used
   DSP                6/8            75% used
   I2C                0/2             0% used
   HFOSC              1/1           100% used
   LFOSC              0/1             0% used
   LEDDA_IP           0/1             0% used
   RGBA_DRV           1/1           100% used
   FILTER             0/2             0% used
   SRAM               1/4            25% used
   WARMBOOT           0/1             0% used
   SPI                0/2             0% used
   EBR               11/30           36% used
   PLL                1/1           100% used
   RGBOUTBUF          3/3           100% used
   I3C                0/2             0% used
   OPENDRAIN          0/3             0% used

Pin Constraint Summary:
   31 out of 31 pins locked (100% locked).
Finished Placer Phase 0 (HIER).  CPU time: 4 secs , REAL time: 5 secs 


....................
Finished Placer Phase 0 (AP).  CPU time: 15 secs , REAL time: 15 secs 

Starting Placer Phase 1. REAL time: 15 secs 
..  ..
....................

Placer score = 4733777.

Device SLICE utilization summary after final SLICE packing:
   SLICE           2132/2640         80% used

WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: There are multiple clocks defined on &apos;hi_clock_gen_inst/CLKHF&apos;. Clock &apos;clk&apos; is used, others are ignored.
WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_R]&apos; with non-SLICE and non-I/O type instance &apos;LED_R&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_G]&apos; with non-SLICE and non-I/O type instance &apos;LED_G&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_B]&apos; with non-SLICE and non-I/O type instance &apos;LED_B&apos;.

WARNING - par: Unable to find the instance/port &apos;BUT_USER&apos; in the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;, the locate object is not specified

WARNING - par: Unable to find the instance/port &apos;BUT_TRIG&apos; in the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;, the locate object is not specified

Finished Placer Phase 1.  CPU time: 1 mins , REAL time: 1 mins 1 secs 

Starting Placer Phase 2.
.

Placer score =  2804590
Finished Placer Phase 2.  CPU time: 1 mins 2 secs , REAL time: 1 mins 3 secs 



<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>

Global Clocks :
  PRIMARY &quot;clk&quot; from comp &quot;hi_clock_gen_inst&quot; on site &quot;HFOSC_R1C32&quot;, clk load = 6, ce load = 0, sr load = 0
  PRIMARY &quot;ADC_DCLK_c&quot; from comp &quot;ADC_DCLK&quot; on CLK_PIN site &quot;44 (PL7B)&quot;, clk load = 1197, ce load = 0, sr load = 0
  PRIMARY &quot;m_axil_rdata_31__N_57&quot; from Q1 on comp &quot;SLICE_3816&quot; on site &quot;R12C2A&quot;, clk load = 0, ce load = 0, sr load = 533
  PRIMARY &quot;maxfan_replicated_net_517&quot; from Q1 on comp &quot;SLICE_4123&quot; on site &quot;R10C2A&quot;, clk load = 0, ce load = 0, sr load = 268
  PRIMARY &quot;i2s_clk_c&quot; from comp &quot;i2s_clk&quot; on PIO site &quot;26 (PR19A)&quot;, clk load = 13, ce load = 0, sr load = 0
  PRIMARY &quot;RPI_SCLK_c_derived_20&quot; from F0 on comp &quot;SLICE_3560&quot; on site &quot;R13C2D&quot;, clk load = 12, ce load = 0, sr load = 0

  PRIMARY  : 6 out of 8 (75%)




I/O Usage Summary (final):
   31 out of 56 (55.4%) I/O sites used.
   31 out of 36 (86.1%) bonded I/O sites used.
   Number of I/O comps: 31; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+----------------+------------+------------+------------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+----------------+------------+------------+------------+
| 0        | 12 / 14 ( 85%) | 3.3V       |            |            |
| 1        | 11 / 14 ( 78%) | 3.3V       |            |            |
| 2        | 8 / 8 (100%)   | 3.3V       |            |            |
+----------+----------------+------------+------------+------------+

Total Placer CPU time: 1 mins 2 secs , REAL time: 1 mins 3 secs 

Writing design to file fft_adc_impl_1_par.dir/5_85.udb ...

WARNING - par: Top module port &apos;BUT_USER&apos; does not connect to anything.
WARNING - par: Top module port &apos;BUT_TRIG&apos; does not connect to anything.
WARNING - par: The clock port [i2s_clk] is assigned to a non clock dedicated pin [26], which might affect the clock performance. Use dedicated clock resources for the port.
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: There are multiple clocks defined on &apos;hi_clock_gen_inst/CLKHF&apos;. Clock &apos;clk&apos; is used, others are ignored.
WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_R]&apos; with non-SLICE and non-I/O type instance &apos;LED_R&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_G]&apos; with non-SLICE and non-I/O type instance &apos;LED_G&apos;.

WARNING - par: Ignore constraint &apos;ldc_set_port -iobuf {} [get_ports LED_B]&apos; with non-SLICE and non-I/O type instance &apos;LED_B&apos;.

WARNING - par: Unable to find the instance/port &apos;BUT_USER&apos; in the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {25} [get_ports BUT_USER]&apos;, the locate object is not specified

WARNING - par: Unable to find the instance/port &apos;BUT_TRIG&apos; in the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;

WARNING - par: In the constraint &apos;ldc_set_location -site {31} [get_ports BUT_TRIG]&apos;, the locate object is not specified


Start NBR router at Wed Sep 23 23:42:40 MSK 2020

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in timing report. You should always run the timing    
      tool to verify your design.                                
*****************************************************************

WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: There are multiple clocks defined on &apos;hi_clock_gen_inst/CLKHF&apos;. Clock &apos;clk&apos; is used, others are ignored.
Start NBR router at Wed Sep 23 23:42:40 MSK 2020

Starting routing resource preassignment
WARNING - par: Certain loads of primary clock signal clk could not be routed to the primary clock tree with dedicated routing resources. This clock may suffer from excessive skew or delay.
Preassignment Summary:
--------------------------------------------------------------------------------
2184 connections routed with dedicated routing resources
6 global clock signals routed
4212 connections routed (of 16948 total) (24.85%)
---------------------------------------------------------
Clock routing summary:
Primary clocks (6 used out of 8 available):
#0  Signal &quot;m_axil_rdata_31__N_57&quot;
       Control loads: 533   out of   533 routed (100.00%)
       Data    loads: 0     out of    82 routed (  0.00%)
#1  Signal &quot;ADC_DCLK_c&quot;
       Clock   loads: 1197  out of  1197 routed (100.00%)
#2  Signal &quot;i2s_clk_c&quot;
       Clock   loads: 13    out of    13 routed (100.00%)
#4  Signal &quot;clk&quot;
       Clock   loads: 5     out of     6 routed ( 83.33%)
#5  Signal &quot;RPI_SCLK_c_derived_20&quot;
       Clock   loads: 12    out of    12 routed (100.00%)
#6  Signal &quot;maxfan_replicated_net_517&quot;
       Control loads: 268   out of   268 routed (100.00%)
       Data    loads: 0     out of    93 routed (  0.00%)
Other clocks:
    Signal &quot;treg_7__N_941&quot;
       Clock   loads: 0     out of     6 routed (  0.00%)
    Signal &quot;pll_adc_inst.lscc_pll_inst.feedback_w&quot;
       Clock   loads: 1     out of     1 routed (100.00%)

---------------------------------------------------------
--------------------------------------------------------------------------------
Completed routing resource preassignment
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: There are multiple clocks defined on &apos;hi_clock_gen_inst/CLKHF&apos;. Clock &apos;clk&apos; is used, others are ignored.

Start NBR section for initial routing at Wed Sep 23 23:42:45 MSK 2020
Level 1, iteration 1
39(0.01%) conflicts; 12092(71.35%) untouched conns; 2054332 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.761ns/-2054.333ns; real time: 6 secs 
Level 2, iteration 1
77(0.03%) conflicts; 10620(62.66%) untouched conns; 3228785 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.721ns/-3228.786ns; real time: 9 secs 
Level 3, iteration 1
99(0.04%) conflicts; 8214(48.47%) untouched conns; 3696033 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.721ns/-3696.034ns; real time: 13 secs 
Level 4, iteration 1
433(0.17%) conflicts; 0(0.00%) untouched conn; 3794607 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -7.145ns/-3794.608ns; real time: 24 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing at Wed Sep 23 23:43:04 MSK 2020
Level 4, iteration 1
178(0.07%) conflicts; 0(0.00%) untouched conn; 3597223 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.125ns/-3597.224ns; real time: 27 secs 
Level 4, iteration 2
101(0.04%) conflicts; 0(0.00%) untouched conn; 3553070 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.125ns/-3553.071ns; real time: 28 secs 
Level 4, iteration 3
59(0.02%) conflicts; 0(0.00%) untouched conn; 3590908 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.085ns/-3590.909ns; real time: 30 secs 
Level 4, iteration 4
24(0.01%) conflicts; 0(0.00%) untouched conn; 3590908 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.085ns/-3590.909ns; real time: 30 secs 
Level 4, iteration 5
14(0.01%) conflicts; 0(0.00%) untouched conn; 3566445 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.085ns/-3566.446ns; real time: 31 secs 
Level 4, iteration 6
10(0.00%) conflicts; 0(0.00%) untouched conn; 3566445 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.085ns/-3566.446ns; real time: 31 secs 
Level 4, iteration 7
6(0.00%) conflicts; 0(0.00%) untouched conn; 3636320 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.085ns/-3636.321ns; real time: 31 secs 
Level 4, iteration 8
3(0.00%) conflicts; 0(0.00%) untouched conn; 3636320 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.085ns/-3636.321ns; real time: 31 secs 
Level 4, iteration 9
2(0.00%) conflicts; 0(0.00%) untouched conn; 3644954 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.390ns/-3644.955ns; real time: 32 secs 
Level 4, iteration 10
2(0.00%) conflicts; 0(0.00%) untouched conn; 3644954 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.390ns/-3644.955ns; real time: 32 secs 
Level 4, iteration 11
0(0.00%) conflict; 0(0.00%) untouched conn; 3646862 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.390ns/-3646.863ns; real time: 32 secs 

Start NBR section for performance tuning (iteration 1) at Wed Sep 23 23:43:12 MSK 2020
Level 4, iteration 1
2(0.00%) conflicts; 0(0.00%) untouched conn; 3645142 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.390ns/-3645.143ns; real time: 32 secs 
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 3648066 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.390ns/-3648.067ns; real time: 32 secs 

Start NBR section for re-routing at Wed Sep 23 23:43:12 MSK 2020
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 3648066 (nbr) score; 
Estimated worst slack/total negative slack&lt;setup&gt;: -6.390ns/-3648.067ns; real time: 33 secs 

Start NBR section for post-routing at Wed Sep 23 23:43:13 MSK 2020
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING - par: There are multiple clocks defined on &apos;hi_clock_gen_inst/CLKHF&apos;. Clock &apos;clk&apos; is used, others are ignored.

End NBR router with 0 unrouted connection


<A name="par_nbrsum"></A><B><U><big>NBR Summary</big></U></B>
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 1869 (11.03%)
  Estimated worst slack&lt;setup&gt; : -6.390ns
  Timing score&lt;setup&gt; : 679312
-----------
Notes: The timing info is calculated for SETUP only.


Total CPU time 35 secs 
Total REAL time: 36 secs 
Completely routed.
End of route.  16948 routed (100.00%); 0 unrouted.
WARNING - par: Top module port &apos;BUT_USER&apos; does not connect to anything.
WARNING - par: Top module port &apos;BUT_TRIG&apos; does not connect to anything.
WARNING - par: The clock port [i2s_clk] is assigned to a non clock dedicated pin [26], which might affect the clock performance. Use dedicated clock resources for the port.

Writing design to file fft_adc_impl_1_par.dir/5_85.udb ...


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = -6.390
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 679.312
PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = 2.596
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0

Total CPU  Time: 1 mins 42 secs 
Total REAL Time: 1 mins 42 secs 
Peak Memory Usage: 415 MB


par done!

Note: user must run &apos;timing&apos; for timing closure signoff.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.



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<DIV id="toc" class="radiant"><span onmousemove="showTocList()">Contents</span>
<UL id="toc_list">
<LI><A href=#par_cts>Cost Table Summary</A></LI>
<LI><A href=#par_best>Best Par Run</A></LI>
<LI><A href=#par_dus>Device utilization summary</A></LI>
<LI><A href=#par_clk>Clock Report</A></LI>
<LI><A href=#par_nbrsum>NBR Summary</A></LI>
</UL>
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